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rev. b - november 10, 2000 1 preliminary t80c5111 low-pin-count 8-bit microcontroller with a/d converter 1. description the t80c5111 is a high performance rom/otp version of the 80c51 8-bit microcontroller in low pin count package. the t80c5111 retains all the features of the standard 80c51 with 4 kbytes rom/otp program memory, 256 bytes of internal ram, a 8-source , 4-level interrupt system, an on-chip oscillator and two timer/counters. the t80c5111 is dedicated for analog interfacing applications. for this, it has an 10-bit, 8 channels a/d converter and a five channels programmable counter array. in addition, the t80c5111 has a hardware watchdog timer with its own low power oscillator, a versatile serial channel that facilitates multiprocessor communication (euart) with an independent baud rate generator, a spi serial bus controller and a x2 speed improvement mechanism. the x2 feature allows to keep the same cpu power at a divided by two oscillator frequency. the prescaler allows to decrease cpu and peripherals clock frequency. the fully static design of the t80c5111 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the t80c5111 has 3 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the peripherals are still operating. in the quiet mode, the a/d converter only is operating. in the power-down mode the ram is saved and all other functions are inoperative. two oscillators source, crystal and rc, provide a versatile power management. the t80c5111 is proposed in low pin count packages. port 0 and port 2 (address / data busses) are not available . 2. features 80c51 compatible three i/o ports two 16-bit timer/counters 256 bytes ram 4 kbytes rom/otp program memory with 64 bytes encryption array and 3 security levels. high-speed architecture 33mhz @ 5v (66 mhz equivalent) 20mhz @ 3v (40 mhz equivalent) x2 speed improvement capability (6 clocks/ machine cycle) 10-bit, 8 channels a/d converter voltage reference for a/d & external analog hardware watchdog timer with integrated low power oscillator (20 m a). programmable i/o mode: standard c51, input only, push-pull, open drain. asynchronous port reset, power on reset, power fail detect full duplex enhanced uart with baud rate generator spi, master/slave mode dual system clock crystal or ceramic oscillator with hardware set up (32 khz or 33/40 mhz) internal rc oscillator (12 mhz) programmable prescaler active oscillator during reset defined by hardware set up timer 0 subclock mode for real time clock. programmable counter array with high speed output, compare / capture, pulse width modulation and watchdog timer capabilities interrupt structure with: 8 interrupt sources, 4 interrupt priority levels power control modes: idle mode power-down mode power-off flag, power fail detect, power on reset power supply: 2.7 to 5.5v temperature ranges: commercial (0 to 70 o c) and industrial (-40 to 85 o c)
2 rev. b - november 10, 2000 preliminary t80c5111 package: ssop16, so24, dil24, (ssop24, so20, under evaluation) 3. block diagram timer 0 int ram 256 t0 t1 rxd txd xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 c51 core (2) (3) (2) (3) port 1 port 3 parallel i/o ports p1 p4 ib-bus watch dog vss vcc (2) (2) (1): alternate function of port 1 (2): alternate function of port 3 rom /otp 4 k *8 x8 eci cex0-4 xtal osc rc osc (1) (1) (3): alternate function of port 4 port 4 p3 (2) (2) (2) pca miso (3) mosi (3) spsck (3) spi rc osc brg ss (3) rst/vpp a/d converter vref ain0-7 (3) vref generator
rev. b - november 10, 2000 3 preliminary t80c5111 4. alias sfr mapping the special function registers (sfrs) of the t80c5111 belongs to the following categories: c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 i/o port registers: p1, p3, p4, p1m1, p1m2, p3m1, p3m2, p4m1, p4m2 timer registers: tcon, th0, th1, tmod, tl0, tl1 serial i/o port registers: saddr, saden, sbuf, scon, brl, bdrcon power and clock control registers: ckcon0, ckcon1, osccon, cksel, pcon, ckrl interrupt system registers: ie, ie1, ipl0, ipl1, iph0, iph1 watchdog timer: wdtrst, wdtprg spi: spcon, spsta, spdat pca: ccap0l, ccap1l, ccap2l, ccap3l, ccap4l, ccap0h, ccap1h, ccap2h, ccap3h, ccap4h, ccapm0, ccapm1, ccapm2, ccapm3, ccapm4, cl, ch, cmod, ccon adc: adccon, adcclk, adcdath, adcdatl, adcf table 1. sfr addresses and reset values notes: "c", value defined by the configuration byte, see section configuration byte, page 10 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h xxxx xxxx ccap1h xxxx xxxx ccap2h xxxx xxxx ccap3h xxxx xxxx ccap4h xxxx xxxx ffh f0h b 0000 0000 adclk 0000 0000 adcon 0000 0000 addl xxxxxx00 addh 0000 0000 adcf 0000 0000 f7h e8h cl 0000 0000 ccap0l xxxx xxxx ccap1l xxxx xxxx ccap2l xxxx xxxx ccap3l xxxx xxxx ccap4l xxxx xxxx conf 1111 111x efh e0h acc 0000 0000 p1m2 0000 0000 p3m2 0000 0000 p4m2 0000 0000 e7h d8h ccon 00x0 0000 cmod x000 0000 ccapm0 00xx x000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 p1m1 0000 0000 p3m1 0000 0000 p4m1 0000 0000 d7h c8h cfh c0h p4 1111 1111 spcon 0001 0100 spsta xxxxxxxx spdat xxxx xxxx c7h b8h ipl0 0000 0000 saden 0000 0000 bfh b0h p3 1111 1111 ie1 0000 0000 ipl1 0000 0000 iph1 0000 0000 iph0 x000 0000 b7h a8h ie0 0000 0000 saddr 0000 0000 ckcon1 xxxx xxx0 afh a0h auxr1 xxxxxxx0 wdrst 0000 0000 wdtprg 0000 0000 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon 0000 0000 9fh 90h p1 1111 1111 ckrl 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckcon0 x000x000 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 cksel xxxx xxxc osccon xxxx xxcc pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
4 rev. b - november 10, 2000 preliminary t80c5111 5. pin configuration mnemonic type name and function v ss i ground: 0v reference v cc i power supply: this is the power supply voltage for normal, idle and power- down operation. vref i/o vref : a/d converter positive reference input, output of the internal voltage reference p1.2-p1.7 i/o port 1: port 1 is an 6-bit programmable i/o port .see section 9, page 21 for a description of i/o ports. alternate functions for port 1 include: i/o eci (p1.2): external clock for the pca i/o cex0 (p1.3): capture/compare external i/o for pca module 0 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 i/o cex3 (p1.6): capture/compare external i/o for pca module 3 i/o cex4 (p1.7): capture/compare external i/o for pca module 4 p3.4/xtal1 p1.7/cex4 p4.7/ain7 1 vcc p1.6/cex3 p3.1/txd p1.3/cex0 p1.2/eci p1.4/cex1 p4.4/miso/ain4 p4.6/spsck/ain6 p4.5/mosi/ain5 p4.3/ int1 /ain3 p4.2/ ss/ain2 p4.1/ain1/t1 p4.0/ain0 p3.0/rxd 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p1.5/cex2 p3.3/t0 p3.2/ int0 so24 dil24 vref vss p3.6/ rst/vpp p3.5/xtal2 p3.4/xtal1 vcc vss 1 p3.6/ rst/vpp p3.5/xtal2 p1.4/cex1 p3.3/t0 p3.2/ int0 p4.4/ain4 vref p4.6/ain6 p4.1 / ain1 /t1 p4.0/ain0 p3.0/rxd p3.1/txd p1.3/cex0 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssop16 p3.5/xtal2 p3.4/xtal1 p1.6/cex3 vref 1 vcc p1.3/cex0 p1.5/cex2 p1.4/cex1 p3.2/ int0 p4.4/miso/ain4 p4.6/spsck/ain6 p4.5/mosi/ain5 p4.2/ ss/ain2 p4.1/ain1 /t1 p4.0/ain0 p3.0/rxd p3.1/txd 2 3 4 5 6 7 8 9 10 20 19 18 27 26 15 14 13 12 11 p3.3/t0 so20* vss p3.6/ rst/vpp p3.5/xtal2 p3.4/xtal1 vref 1 avcc p1.6/cex3 p3.1/txd p1.3/cex0 p1.2/eci p1.4/cex1 p4.4/miso/ain4 p4.6/spsck/ain6 p4.5/mosi/ain5 p4.3/ int1 /ain3 p4.2/ ss/ain2 p4.1/ain1/t1 p4.0/ain0 p3.0/rxd 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p1.5/cex2 p3.3/t0 p3.2/ int0 ssop24* vss avss vcc p3.6/ rst/vpp * under evaluation
rev. b - november 10, 2000 5 preliminary t80c5111 p3.0-p3.6 i/o port 3: port 3 is an 7-bit programmable i/o port with internal pull-ups. see section 9, page 21 for a description of i/o ports. port 3 also serves the special features of the 80c51 family, as listed below. i/o rxd (p3.0): serial input port i/o txd (p3.1): serial output port i/o int0 (p3.2): external interrupt 0 i/o t0 (p3.3): timer 0 external input i/o xtal1 (p3.4): input to the inverting oscillator amplifier and input to the internal clock generator circuits, selected by hardware set up a i/o xtal2 (p3.5): output from the inverting oscillator amplifier, selected by hardware set up i rst/vpp (p3.6 is not implemented on first version): reset/programming supply voltage: a low on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v cc permits a power-on reset using only the internal ( selected by hardware set up) or an external capacitor to v ss. this pin also receives the 12v programming pulse which will start the eprom programming and the manufacturer test modes. p4.0-p4.7 i/o port 4 : port 4 is an 8-bit programmable i/o port with internal pull-ups. see section 9, page 21 for a description of i/o ports. port 4 is also the input port of the analog to digital converter i/o ain0 (p4.0): a/d converter input 0 i/o ain1 (p4.1): a/d converter input 1 t1: timer 1 external input i/o ain2 (p4.2): a/d converter input 2 ss: slave select input of the spi controller i/o ain3 (p4.3): a/d converter input 3 int1: external interrupt 1 i/o ain4 (p4.4): a/d converter input 4 miso: master in, slave out of the spi controller i/o ain5 (p4.5): a/d converter input 5 mosi: master out, slave in of the spi controllers i/o ain6 (p4.6): a/d converter input 6 spsck: clock i/o of the spi controlle i/o ain7 (p4.7): a/d converter input 7 a. hardware set up : +configuration bits programmed with the code for rom version +configuration bits for eprom version
6 rev. b - november 10, 2000 preliminary t80c5111 6. clock system 6.1. overview the t80c5111 oscillator system provides a reliable clocking system with full mastering of speed versus cpu power trade off. several clocks sources are possible: external clock input high speed crystal or ceramic oscillator low speed crystal oscillator integrated high speed rc oscillator the low speed rc oscillator of the watchdog is a backup clocking source when no clock are selected in active or idle modes. the selected clock source can be divided by 2-512 before clocking the cpu and the peripherals. when x2 function is set, the cpu need 6 clock periods per cycle. active oscillator at reset is defined by bits in a configuration byte programmed on an otp programmer or by metal mask. clocking is controlled by several sfr registers : oscon, ckcon0, ckcon1, ckrl. 6.2. blocks description the t80c5111 includes the following oscillators: crystal oscillator, with two possible gains optimized for 32 khz or 33 mhz. integrated high speed rc oscillator, with typical frequency of 12 mhz integrated low speed, low power rc oscillator, with typical frequency of 200 khz; this oscillator is used to clock the hardware watchdog and as back up oscillator when the cpu receives no clock signal in active or idle modes. 6.2.1. crystal oscillator : osca the crystal oscillator uses two external pins, xtal1 for input and xtal2 for output. xt_sp in configuration byte allows to select between two possible gains optimized for 32 khz or 33 mhz. both crystal and ceramic resonnators can be used. oscaen in osccon register is an enable signal for the crystal oscillator or the external oscillator input. when the crystal oscillator is not selected, xtal1 can be used as a standard c51 i/o port, and x2 can be used as a standard c51 i/o port. 6.2.2. integrated high speed rc oscillator : oscb the high speed rc oscillator do not need any external component; its typical frequency is 12 mhz. note that the on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use in some applications. oscben in osccon register is an enable signal for the high speed rc oscillator.
rev. b - november 10, 2000 7 preliminary t80c5111 6.2.3. integrated low speed, low power rc oscillator : oscc the low speed, low power rc oscillator is used to clock the hardware watchdog and do not need any external component; its typical frequency is 200 khz. this oscillator is also used as back up oscillator when the cpu receive no clock signal in active or idle modes. rclf_off is the configuration bit used to switch on or off the low speed rc oscillator. note that the on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use in some applications. 6.2.4. clock selector cks bit in cks register is used to select from crystal to rc oscillator. oscben bit in osccon register is used to enable the rc oscillator. oscaen bit in osccon register is used to enable the crystal oscillator or the external oscillator input. if both oscillators are disabled, the low speed oscillator, oscc is used as a backup source for the cpu and the peripherals. this feature provides a stand alone low frequency mode which can be activated when needed. 6.2.5. clock prescaler before supplying the cpu and the peripherals, the main clock is divided by a factor to 2 to 512, as defined by the ckrl register. the cpu needs from 12 to 256*12 clock periods per instruction. this allows: to accept any cyclic ratio to be accepted on xtal1 input. to reduce the cpu power consumption. the x2 bit allows to bypass the clock prescaler ; in this case, the cpu need only 6 clock periods per machine cycle. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%
8 rev. b - november 10, 2000 preliminary t80c5111 6.3. functional block diagram figure 1. functional block diagram 6.4. operating modes 6.4.1. reset : an hardware reset select xtal_osc or rc_osc depending on the rst_osc configuration bit 6.4.2. functional modes : 6.4.2.1. normal modes : cpu and peripherals clock depend on the software selection using ckcon0, ckcon1, cksel and ckrl registers cks bit selects either xtal_osc or rc_osc ckrl register determines the frequency of the selected clock, unless x2 bit is set. in this case the prescaler/divider is not used, so cpu core needs only 6-clock period per machine cycle. according to the value of the peripheral x2 individual bit, each peripherals need 6 or 12 clock period per instructions. it is always possible to switch dynamicaly by software from xtal_osc to rc_osc, and vice versa by changing cks bit, a synchronization cell allowing to avoid any spike during transition. xtal2 xtal1 pwdrc wd clock pwdosc ckrl reload 8-bit prescaler-divider resetb 1 0 oscout xtal_osc rc_osc xt_sp oscben oscaen cks x2 0 1 1 0 rclf_osc rclf_off mux filter + rclf_off osca oscb oscc ckidle ck idle cpu clock peripherals clock pwd ckout ckadc quiet oscben oscaen 0 1 :128 a/d clock sub clock timer 0 clock
rev. b - november 10, 2000 9 preliminary t80c5111 6.4.2.2. idle modes : idle modes are achieved by using any instruction that writes into pcon.0 sfr idle modes a and b depend on previous software sequence, prior to writing into pcon.0 register : idle mod e a : xtal_osc is running (oscaen = 1) and selected (cks = 1) idle mod e b : rc_osc is running (oscben = 1) and selected (cks = 0) the unused oscillator xtal_osc or rc_osc can be stopped by software by clearing oscaen or oscben respectively. exit from idle mode is acheived by reset, or by activation of an enabled interrupt. in both case, pcon.0 is cleared by hardware. exit from idle modes will leave the ocillators control bits oscaen, oscben and cks unchanged. 6.4.2.3. power down modes : power down modes are achieved by using any instruction that writes into pcon.1 sfr exit from power down mode is acheived either by an harware reset, by an external interruption. by rst signal : the cpu will restart in the mode defined by rst_osc. by int0 or int1 interruptions, if enabled. the ocillators control bits oscaen, oscben and cks will not be changed, so the selected oscillator before entering into power-down will be activated. 6.4.2.4. prescaler divider : an hardware reset selects the prescaler divider : ckrl = ffh: internal clock = oscou t / 2 (standard c51 feature) x2=0, sel_osc signal selects xtal_osc or rc_osc, depending on the value of the rst_osc configuration bit. after reset, any value between ffh down to 00h can be written by software into ckrl sfr in order to divide frequency of the selected oscillator: ckrl = 00h : minimum frequency = oscout / 512 ckrl = ffh : maximum frequency = oscout / 2 pd idle cks oscben oscaen rclf _off selected mode comment 0 0 1 x 1 x normal mode a osca: xtal clock x x 1 x 0 1 invalid no active clock 0 0 1 0 0 0 rescue mode oscc: low speed rc clock active 0 0 0 1 x x normal mode b, oscb: high speed rc clock x x 0 0 x 1 invalid 0 0 0 0 0 0 rescue mode oscc: low speed rc clock active 0 1 1 x 1 x idle mode a the cpu is off, osca supplies the peripherics 0 1 0 1 x x idle mode b the cpu is off, oscb supplies the peripherics 1xx x 1 0 power down mode with wd the cpu and peripherics are off, but oscc is still running for wd 1 x x x x 1 total power down the cpu is off, osca and oscb are stopped oscc is stopped
10 rev. b - november 10, 2000 preliminary t80c5111 a software instruction which set x2 bit desactivates the precaler/divider, so the internal clock is either xtal_osc or rc_osc depending on sel_osc bit. 6.5. timer 0 : clock inputs figure 2. time r 0 : clock inputs the sclkt0 bit in osccon register allows to select timer 0 subsidiary clock. this allow to perform a real time clock function. sclkt 0=0: timer 0 uses the standard t0 pin as clock input ( standard mode ) sclkt 0=1: timer 0 uses the special sub clock as clock input. when the subclock input is selected for timer 0 and the crystal oscillator is selected for cpu and peripherals, the ckrl prescaler must be set to ff (division factor 2) in order to assure a proper count on timer 0. with a 32 khz crystal, the timer interrupt can be set from 1/256 to 256 seconds to perform a real time clock (rtc) function. the power consumption will be very low as the cpu is in idle mode at 32 khz most of the time. when more cpu power is needed, the internal rc oscillator is activated and used by the cpu and the others peripherals. 6.6. registers 6.6.1. configuration byte the configuration byte is a special register. its content is defined by the diffusion mask in the rom version or is rerad or written by the otp programmer in the otp version. this register can also be accessed as a read only register. conf - con?guration byte (efh) 7 6 5 4 3 2 1 0 lb1 lb2 lb3 rst_osc xt_sp rst_ext oscc_off bit number bit mnemonic description 7:5 - program memory lock bits see chapter program memory for the de?nition of these bits.. sclkt0 1 0 ckidle :6 t0 pin sub clock c/ t 1 0 osccon tmod gate int0 tr0 timer 0 control
rev. b - november 10, 2000 11 preliminary t80c5111 initial value after erasing : 1111 111x 6.6.2. clock control register the clock control register is used to define the clock system behavior osccon - clock control register (86h) reset value = 0xxx x0 "rst_osc" "rst_osc" b not bit addressable 4 rst_osc selected oscillator at reset this bit is used to de?ne the value of some bits controlling the oscillator activity at reset: 1: the crystal oscillator is sectected and active 0: the rc oscillator is selected; it is also active if the wdrc is inactive. 3 xt_sp crystal oscillator speed this bit is used to de?ne the performance of the crystal oscillator. 1: high speed, up to 33 mhz 0: low speed, low power, optimised for 32 khz. 2 ext_rst external reset this bit de?nes the behavior of the p3.6/ rst pin 1: p3.6/ rst is the reset pin 0: p3.6/ rst is an input pin 1 oscc_off control for watchdog rc oscillator this bit is used to switch the watchdog rc oscillator and the watchdog source 1: wdrc oscillator is off; the watchdog is clocked by the main oscillator. 0: wdrc oscillator is on and clock the watchdog 0 - reserved the value read from this bit is indeterminate. do not reset this bit. 7 6 5 4 3 2 1 0 - - - - - sclkt0 oscben oscaen bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 sclkt0 sub clock timer0 cleared by software to select t0 pin set by software to select t0 sub clock 1 oscben enable rc oscillator this bit is used to enable the high speed rc oscillator 0: the oscillator is disabled 1: the oscillator is enabled. 0 oscaen enable crystal oscillator this bit is used to enable the crystal oscillator 0: the oscillator is disabled 1: the oscillator is enabled. bit number bit mnemonic description
12 rev. b - november 10, 2000 preliminary t80c5111 6.6.3. clock selection register the clock selectionl register is used to define the clock system behavior cksel - clock selection register (85h) reset value = xxxx xxx "rst_osc" b not bit addressable 6.6.4. clock prescaler register this register is used to reload the clock prescaler of the cpu and peripheral clock. ckrl - clock prescaler register (97h) reset value = 1111 1111b not bit addressable 6.6.5. clock control register this register is used to control the x2 mode of the cpu and peripheral clock. table 2. ckcon0 register 7 6 5 4 3 2 1 0 - - - - - - cks bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 cks active oscillator selection this bit is used to select the active oscillator 1: the crystal oscillator is selected 0: the high speed rc oscillator is selected. 7 6 5 4 3 2 1 0 m bit number bit mnemonic description 7:0 ckrl 0000 0000b: division factor equal 512 1111 1111b: division factor equal 2 m: division factor equal 2*(256-m)
rev. b - november 10, 2000 13 preliminary t80c5111 ckcon0 - clock control register (8fh) reset value = x000 0000b not bit addressable table 3. ckcon1 register ckcon1 - clock control register reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - wdx2 pcax2 six2 - t1x2 t0x2 x2 bit number bit mnemonic description 7 - reserved 6 wdx2 watchdog clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5 pcax2 programmable counter array clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4 six2 enhanced uart clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3 - reserved 2 t1x2 timer1 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 1 t0x2 timer0 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 0 x2 cpu clock clear to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6clock periods per machine cycle (x2 mode) and to enable the individual peripherals "x2" bits. 7 6 5 4 3 2 1 0 - - - - - - brgx2 spix2 bit number bit mnemonic description 7 - reserved 6 - reserved 5 - reserved 4 - reserved 3 - reserved 2 - reserved 1 - reserved 0 spix2 spi clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle
14 rev. b - november 10, 2000 preliminary t80c5111 7. reset and power management 7.1. introduction the power monitoring and management can be used to supervise the power supply (vdd) and to start up properly when t80c5111 is powered up. it consists of the features listed below and explained hereafter: power on reset power-fail reset power-off flag idle mode power-down mode reduced emi mode all these features are controlled by several registers, the power control register (pcon) and the auxiliary register (auxr) detailed at the end of this chapter. aux register not available on all versions. 7.2. functional description figure 3 shows the block diagram of the possible sources of microcontroller reset.
rev. b - november 10, 2000 15 preliminary t80c5111 figure 3. reset sources notes: rst pin available only on 48 and 52 pins versions. notes: rst pin available only on lpc versions. 7.3. power-on reset the t80c5111 has a power on reset (por) module which reset the chip during the initial power raise. the internal power on reset pulse duration is 24 clock periods of the cpu clock. the chip can also be reseted by the p3.6/ rst/vpp pin provided the ext_rst bit of the configuration byte is high. this module set the pof bit vhen vcc is below the memory data retention voltage. the behavior or por and pfd is shown on figure 4. 7.4. power-fail detector the power-fail detector (pfd) is controlled by rstd bit in pcon register. the pfd is disabled upon reset. when enabled, the power supply is continuously monitored and an internal reset is generated (1) if vdd goes below v rst for at least 60 ns. if the power supply rises again over v rst+ ( 2 ), the internal reset completes after 24 cpu clock periods. if rstd is reset, the power supply monitoring is disabled. rst_ext reset rst pin* conf cpu clock +24 ck hardware wd por pca wd rst pin* pfd en fail 5v rstd pcon pof pcon set
16 rev. b - november 10, 2000 preliminary t80c5111 in power-down mode, the pfd is automatically disabled; this avoids extra consumption and allows vdd reduction to v ret. note: 1. the internal reset is not propagated on the rst pin. 2 see ac/dc section for the speci?cations of vrst. caution: when vdd is reduced to v ret in power-down mode the vdd voltage is not accuratly monitored. in this case, ram content may be damage if vdd goes below v ret and circuit behavior is unpredictable unless an external reset is applied. the pof bit can be used to verify if memory contains valid data. figure 4. power fail reset timing diagram 7.5. power-off flag when the power is turned off or fails, the data retention is not guaranteed. a power-off flag (pof, see 7.6.1. ) allows to detect this condition. pof is set by hardware during a reset which follows a power-up or a power-fail. this is a cold reset. a warm reset is an external or a watchdog reset without power failure, hence which preserves the internal memory content and pof. to use pof, test and clear this bit just after reset. then it will be set only after a cold reset. notes: when power supply monitoring is disabled (rstd= 1 or in power-down mode), pof information is not delivered with the same accuracy. it is recommended to clear and not to take in account the pof value after exit from a power down mode with vdd reduction. notes: the pof flag is set only if vcc is lower below the memory data retention voltage. hence, the pfd may detect a power fail while the pof bit is still valid. 24 ck rstvpp por pfd rst 24 ck <60ns >60ns v rst+ v rst v ret
rev. b - november 10, 2000 17 preliminary t80c5111 7.6. registers 7.6.1. pcon: power configuration register table 4. pcon register pcon (s:87h) power con?guration register reset value= 0000 0000b 7.7. port pins the value of port pins in the different operating modes is shown on the figure below. table 5. pin conditions in special operating modes 7 6 5 4 3 2 1 0 smod1 smod0 rstd pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 double baud rate bit set to double the baud rate when timer 1 is used and mode 1, 2 or 3 is selected in scon register. 6 smod0 scon select bit when cleared, read/write accesses to scon.7 are to sm0 bit and read/write accesses to scon.6 are to sm1 bit. when set, read/write accesses to scon.7 are to fe bit and read/write accesses to scon.6 are to ovr bit. scon is serial port control register. 5 rstd reset detector disable bit clear to disable the power-fail detector. set to enable the power-fail detector. 4 pof power-off flag s et by hardware when vdd rises above v ret+ to indicate that the power supply has been set off. must be cleared by software. 3 gf1 general purpose flag 1 one use is to indicate wether an interrupt occurred during normal operation or during idle mode. 2 gf0 general purpose flag 0 one use is to indicate wether an interrupt occurred during normal operation or during idle mode. 1 pd power-down mode bit cleared by hardware when an interrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0 idl idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence. mode program memory port 1 pins port 3 pins port 4 pins reset dont care weak high weak high weak high idle internal data data data power-down internal data data data
18 rev. b - november 10, 2000 preliminary t80c5111 8. hardware watchdog timer the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle ( 6 internal clock periods) and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). the t0 bit of the wdtprg register is used to select the overflow after 10 or 14 bits. when wdt overflows, it will generate an internal reset. it will also drive an output reset high pulse at the emulator rst-pin. if the crystal oscillator is selected with whe low speed option (32khz), the low speed rc oscillator must not be used. in this case the wdt will also use the low speed crystal oscillator. 8.1. using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) or 1024 (1fffh) and this will reset the device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst-pin. the reset pulse duration is 96 x t osc , where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capability, ranking from 16ms to 2s @ f osc = 12mhz and t0=0. to manage this feature, refer to wdtprg register description, table 7. (sfr0a7h). table 6. wdtrst register wdtrst address (0a6h) write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 7 6 5 4 3 2 1 reset value x x x x x x x
rev. b - november 10, 2000 19 preliminary t80c5111 table 7. wdtprg register wdtprg address (0a7h) reset value xxx0 0000 write only register 8.1.1. wdt during power down and idle 8.1.1.1. power down and oscc inactive in power down mode the oscillator stops, which means the wdt also stops. while in power down mode the user does not need to service the wdt. there are 2 methods of exiting power down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power down mode. when power down is exited with hardware reset, servicing the wdt should occur as it normally should whenever the t80c5111 is reset. exiting power down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reseted during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is best to reset the wdt just before entering powerdown. 7 6 5 4 3 2 1 0 t4 t3 t2 t1 t0 s2 s1 s0 bit number bit mnemonic description 7 t4 reserved do not try to set this bit. 6 t3 5 t2 4 t1 3 t0 wdt over?ow select bit 0 : over?ow after 14 bits 1 : over?ow after 10 bits 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 s2s1s0 selected t ime-out with t0=0 000 (2 14 - 1) machine cycles, 16.3 ms @ 12 mhz 001 (2 15 - 1) machine cycles, 32.7 ms @ 12 mhz 010 (2 16 - 1) machine cycles, 65.5 ms @ 12 mhz 011 (2 17 - 1) machine cycles, 131 ms @ 12 mhz 100 (2 18 - 1) machine cycles, 262 ms @ 12 mhz 101 (2 19 - 1) machine cycles, 542 ms @ 12 mhz 110 (2 20 - 1) machine cycles, 1.05 s @ 12 mhz 111 (2 21 - 1) machine cycles, 2.09 s @ 12 mhz s2s1 s0 selected t ime-out with t0=1 000 (2 10 - 1) machine cycles, 60 ms @ 200 khz 001 (2 11 - 1) machine cycles, 120ms @ 200 khz 010 (2 12 - 1) machine cycles, 240ms @ 200 khz 011 (2 13 - 1) machine cycles, 480ms @ 200 khz 100 (2 14 - 1) machine cycles, 860ms @ 200 khz 101 (2 15 - 1) machine cycles, 1.7s @ 200 khz 110 (2 16 - 1) machine cycles, 3.4s @ 200 khz 111 (2 17 - 1) machine cycles, 6.8s @ 200 khz
20 rev. b - november 10, 2000 preliminary t80c5111 8.1.1.2. power down and oscc active in power down mode the low speed rc oscillator never stops. if the wdt is active before entering power down, the t80c5111 will be reseted once and will start executing the program code. the software may then decide to leave the wdt inactive. if the high speed rc oscillator is selected at reset, this mode may be used to periodically awake the t80c5111 and check for an external event while keeping the average consumption at a very low level. there are 2 methods of exiting power down mode: by a hardware or watchdog reset or via a level activated external interrupt which is enabled prior to entering power down mode. when power down is exited with hardware or watch dog reset, servicing the wdt should occur as it normally should whenever the t80c5111 is reset. exiting power down with an interrupt is significantly different. as the wdt and interrupt are asynchronous events, the wdt may overflow within a few states of exiting of powerdown. to limit the probability of such an event, it is suggested that the wdt be reseted during the interrupt service routine. 8.1.1.3. idle mode in the idle mode, the oscillator continues to run. to prevent the wdt from resetting the t80c5111 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode.
rev. b - november 10, 2000 21 preliminary t80c5111 9. ports the low pin count versions of the t80c5111 has 3 i/o ports, port 1, port 3, and port 4. the exact number of i/ o pins available depend upon the oscillator and reset options chosen. the number of possible i/o on each package option is shown on table 9. at least 11, 15 or 19 pins of the t80c5111 may be used as i/os when a two-pin external oscillator and an external reset circuit are used. three more pins may be available if fully on-chip oscillator and reset configurations are chosen. notes: (*)not implemeted on first version except rst/vpp, all port1, port3 and port4 i/o port pins on the t80c5111 may be software configured to one of four types on a bit-by-bit basis, as shown in table 10. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input only. two configuration registers for each port choose the output type for each port pin. 9.1. ports types 9.1.1. quasi-bidirectional output configuration the default port output configuration for standard t80c5111 i/o ports is the quasi-bidirectional output that is common on the 80c51 and most of its derivatives. this output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. one of these pull-ups, called the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. the very weak pull- up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the "weak" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull- up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. table 8. number of available i/o versus pin number 16 20 24 i/o 10 14 18 rst input (*) 1 1 1 xtal i/o 2 2 2 maximun i/o count 12+1 16+1 20+1 table 9. port output configurationsettings using pxm1 and pxm2 registers pxm1.y bit pxm2.y bit port output mode 0 0 quasi bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain
22 rev. b - november 10, 2000 preliminary t80c5111 the third pull-up is referred to as the "strong" pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for a brief time, two cpu clocks, in order to pull the port pin high quickly. then it turns off again. the quasi-bidirectional port configuration is shown in figure 5. figure 5. quasi-bidirectional output 9.1.2. open drain output configuration the open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to vdd. the pull-down for this mode is the same as for the quasi- bidirectional mode. the open drain port configuration is shown in figure 6. figure 6. open drain output 9.1.3. push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 7. 2 cpu input pin strong very weak n p p weak p clock delay port latch data data input pin n port latch data data
rev. b - november 10, 2000 23 preliminary t80c5111 figure 7. push-pull output 9.1.4. input only configuration the input only configuration is a pure input with neither pull-up nor pull-down. the input only configuration is shown in figure 7. figure 8. input only 9.2. ports description 9.2.1. ports p1, p3 and p4 p3.7 may be used as a schmitt trigger input if the t80c5111 has been configured for an internal reset and is not using the external reset input function rst. additionally, port pins p3. and p3.5 are disabled for both input and output if one of the crystal oscillator options is chosen. those options are described in the oscillator section. every output on the t80c5111 may potentially be used as a 20 ma sink led drive output. however, there is a maximum total output current for all ports which must not be exceeded. all ports pins of the t80c5111 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approximately 10 ns rise and fall times. the inputs of each i/o port of the t80c5111 are ttl level schmitt triggers with hysteresis. input pin strong n p port latch data data input pin data
24 rev. b - november 10, 2000 preliminary t80c5111 9.2.2. ports p0 and p2 high pin count version of the t80c5111 have standard address and data ports p0 and p2. these ports are standard c51 ports (quasi-bidirectional i/o). the control lines are provided on the pins : ale, psen, ea, reset; rd and wr signals are on the bits p1.1 and p1.0 . 9.3. registers table 10. p1m1 register p1m1 address (d4h) reset value 0000 00xx table 11. p1m2 register p1m2 address (e2h) reset value 0000 00xx table 12. p3m1 register p3m1 address (d5h) reset value 0000 0000 table 13. p3m2 register p3m2 address (e4h) reset value 0000 0000 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 bit number bit mnemonic description 7 : 0 p1m1.x port output con?guration bit see table 10. for con?guration de?nition 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 p1m2.5 p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 bit number bit mnemonic description 7 : 0 p1m2.x port output con?guration bit see table 10. for con?guration de?nition 7 6 5 4 3 2 1 0 p3m1.7 p3m1.6 p3m1.5 p3m1.4 p3m1.3 p3m1.2 p3m1.1 p3m1.0 bit number bit mnemonic description 7 : 0 p3m1.x port output con?guration bit see table 10. for con?guration de?nition 7 6 5 4 3 2 1 0 p3m2.7 p3m2.6 p3m2.5 p3m2.4 p3m2.3 p3m2.2 p3m2.1 p3m2.0 bit number bit mnemonic description 7 : 0 p3m2.x port output con?guration bit see table 10. for con?guration de?nition
rev. b - november 10, 2000 25 preliminary t80c5111 table 14. p4m1 register p4m1 address (d6h) reset value 0000 0000 table 15. p4m2 register p4m2 address (e5h) reset value 0000 0000 7 6 5 4 3 2 1 0 p4m1.7 p4m1.6 p4m1.5 p4m1.4 p4m1.3 p4m1.2 p4m1.1 p4m1.0 bit number bit mnemonic description 7 : 0 p4m1.x port output con?guration bit see table 10. for con?guration de?nition 7 6 5 4 3 2 1 0 p4m2.7 p4m2.6 p4m2.5 p4m2.4 p4m2.3 p4m2.2 p4m2.1 p4m2.0 bit number bit mnemonic description 7: 0 p4m2.x port output con?guration bit see table 10. for con?guration de?nition
26 rev. b - november 10, 2000 preliminary t80c5111 10. dual data pointer register ddptr the additional data pointer can be used to speed up code execution and reduce code size in a number of ways. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 16.) that allows the program code to switch between them (refer to figure 9). figure 9. use of dual pointer external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1
rev. b - november 10, 2000 27 preliminary t80c5111 table 16. auxr1: auxiliary register 1 user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new feature. in that case, the reset value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a source pointer and the other one as a "destination" pointer. 7 6 5 4 3 2 1 0 - - - - - - - dps bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 - reserved the value read from this bit is indeterminate. do not set this bit. 0 dps data pointer selection clear to select dptr0. set to select dptr1.
28 rev. b - november 10, 2000 preliminary t80c5111 assembly language ; block move using dual data pointers ; destroys dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state.
rev. b - november 10, 2000 29 preliminary t80c5111 11. serial i/o ports enhancements the serial i/o ports in the t80c5111 are compatible with the serial i/o port in the 80c52. they provide both synchronous and asynchronous communication modes. they operate as universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o ports include the following enhancements: framing error detection automatic address recognition 11.1. framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 10). figure 10. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 17) bit is set. software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 11. and figure 12.). figure 11. uart timings in mode 1 sm0 to uart mode control (smod0 = 0 for uart) ri ti rb8 tb8 ren sm2 sm1 idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control set fe bit if stop bit is 0 (framing error) (smod 0 = 1 for uart) scon for uart (98h) (scon_1 for uart_1 (c0h)) pcon for uart (87h) (smod bits for uart_1 are located in bdrcon_1) sm0/fe data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1
30 rev. b - november 10, 2000 preliminary t80c5111 figure 12. uart timings in modes 2 and 3 11.2. automatic address recognition the automatic address recognition feature is enabled for each uart when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the devices address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). 11.2.1. given address each uart has an individual address that is specified in saddr register; the saden register is a mask byte that contains dont-care bits (defined by zeros) to form the devices given address. the dont-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr 0101 0110b saden 1111 1100b given 0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a: saddr 1111 0001b saden 1111 1010b given 1111 0x0xb slave b: saddr 1111 0011b saden 1111 1001b given 1111 0xx1b slave c: saddr 1111 0010b saden 1111 1101b given 1111 00x1b ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
rev. b - november 10, 2000 31 preliminary t80c5111 the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a dont-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a dont care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 11.2.2. broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as dont-care bits, e.g.: saddr 0101 0110b saden 1111 1100b broadcast =saddr or saden 1111 111xb the use of dont-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a: saddr 1111 0001b saden 1111 1010b broadcast 1111 1x11b, slave b: saddr 1111 0011b saden 1111 1001b broadcast 1111 1x11b, slave c: saddr= 1111 0010b saden 1111 1101b broadcast 1111 1111b for slaves a and b, bit 2 is a dont care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. 11.2.3. reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all dont-care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. 11.3. baud rate selection for uart for mode 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the t2con and bdrcon registers.
32 rev. b - november 10, 2000 preliminary t80c5111 figure 13. baud rate selection 11.3.1. baud rate selection table for uart 11.3.2. internal baud rate generator (brg) when the internal baud rate generator is used, the baud rates are determined by the brg overflow depending on the brl reload value, the x2 bit in ckon0 register, the value of spd bit (speed mode) in bdrcon register and the value of the smod1 bit in pcon register (for uart). : figure 14. internal baud rate generator tbck rbck clock source for uart tx clock source uart rx 0 0 timer 1 timer 1 1 0 int_brg timer 1 0 1 timer 1 int_brg 1 1 int_brg int_brg / 16 rbck int_brg 0 1 tbck int_brg timer1_brg rx clock / 16 0 1 timer1_brg tx clock peripheral clock brg 0 1 /6 brl /2 0 1 int_brg spd brr smod1 auto reload counter over?ow
rev. b - november 10, 2000 33 preliminary t80c5111 for uart example of computed value when x2=1, smod1=1, spd=1 example of computed value when x2=0, smod1=0, spd=0 the baud rate generator can be used for mode 1 or 3 (refer to figures 13 ), but also for mode 0 for both uarts, thanks to the bit src located in bdrcon register (table 19) 11.4. uarts registers saden - slave address mask register for uart (b9h) reset value = 0000 0000b saddr - slave address register for uart (a9h) reset value = 0000 0000b baud rates f xtal = 16.384 mhz f xtal = 24mhz brl error (%) brl error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - baud rates f osc = 16.384 mhz f osc = 24mhz brl error (%) brl error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 baud_rate = 2 smod1 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x [256 - (brl)] (brl) = 256 - 2 smod1 x 2 x2 x f xtal 2 x 2 x 6 (1-spd) x 16 x baud_rate
34 rev. b - november 10, 2000 preliminary t80c5111 sbuf - serial buffer register for uart (99h) reset value = xxxx xxxxb brl - baud rate reload register for the internal baud rate generator, uart uart(9ah) reset value = 0000 0000b 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
rev. b - november 10, 2000 35 preliminary t80c5111 table 17. scon register scon - serial control register for uart (98h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0=1) for uart clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 (smod0=0) for uart refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6 sm1 serial port mode bit 1 for uart sm0 sm1 mode description baud rate 0 0 0shift registerf xtal /12 (f xtal /6 x2 mode) 0 1 18-bit uartvariable 1 0 29-bit uartf xtal /64 or f xtal /32 (f xtal /32 or f xtal /16 x2 mode) 1 1 39-bit uartvariable 5 sm2 serial port mode 2 bit / multiprocessor communication enable bit for uart clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren reception enable bit for uart clear to disable serial reception. set to enable serial reception. 3 tb8 transmitter bit 8 / ninth bit to transmit in modes 2 and 3 for uart . clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8 receiver bit 8 / ninth bit received in modes 2 and 3 for uart cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1 ti transmit interrupt ?ag for uart clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 ri receive interrupt ?ag for uart clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 11. and figure 12. in the other modes.
36 rev. b - november 10, 2000 preliminary t80c5111 table 18. pcon register pcon - power control register (87h) reset value = 0001 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesnt affect the value of this bit. 7 6 5 4 3 2 1 0 smod1 smod0 rstd pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 for uart set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 for uart clear to select sm0 bit in scon register. set to to select fe bit in scon register. 5 rstd reset detector disable bit clear to disable pfd. set to enable pfd. 4 pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
rev. b - november 10, 2000 37 preliminary t80c5111 table 19. bdrcon register bdrcon - baud rate control register (9bh) reset value = xxx0 0000b 7 6 5 4 3 2 1 0 - - - brr tbck rbck spd src bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit 6 - reserved the value read from this bit is indeterminate. do not set this bit 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 brr baud rate run control bit clear to stop the internal baud rate generator. set to start the internal baud rate generator. 3 tbck transmission baud rate generator selection bit for uart clear to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2 rbck reception baud rate generator selection bit for uart clear to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1 spd baud rate speed control bit for uart clear to select the slow baud rate generator. set to select the fast baud rate generator. 0 src baud rate source select bit in mode 0 for uart clear to select f osc /12 as the baud rate generator (f osc /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
38 rev. b - november 10, 2000 preliminary t80c5111 12. serial port interface (spi) 12.1. introduction the serial peripheral interface module (spi) which allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. 12.2. features features of the spi module include the following: full-duplex, three-wire synchronous transfers master or slave operation eight programmable master clock rates serial clock with programmable polarity and phase master mode fault error flag with mcu interrupt capability write collision flag protection 12.3. signal description figure 15 shows a typical spi bus configuration using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices: figure 15. typical spi bus the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. 12.3.1. master output slave input (mosi) this 1-bit signal is directly connected between the master device and a slave device. the mosi line is used to transfer data in series from the master to the slave. therefore, it is an output signal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb)last. slave 1 miso mosi sck ss miso mosi sck ss port 0 1 2 3 slave 3 miso mosi sck ss slave 4 miso mosi sck ss slave 2 miso mosi sck ss v dd master
rev. b - november 10, 2000 39 preliminary t80c5111 12.3.2. master input slave output (miso) this 1-bit signal is directly connected between the slave device and a master device. the miso line is used to transfer data in series from the slave to the master. therefore, it is an output signal from the slave, and an input signal to the master. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. 12.3.3. spi serial clock (sck) this signal is used to synchronize the data movement both in and out the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. 12.3.4. slave select ( ss) each slave peripheral is selected by one slave select pin ( ss). this signal must stay low for any message for a slave. it is obvious that only one master ( ss high level) can drive the network. the master may select each slave device by software through port pins (figure 15). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. in a master configuration, the ss line can be used in conjunction with the modf flag in the spi status register (spsta) to prevent multiple masters from driving mosi and sck (see error conditions). a high level on the ss pin puts the miso line of a slave spi in a high-impedance state. the ss pin could be used as a general purpose if the following conditions are met: the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin will be pulled low. therefore, the modf flag in the spsta will never be set 1 . the device is configured as a slave with cpha and ssdis control bits set 2 . this kind of configuration can happen when the system comprises one master and one slave only. therefore, the device should always be selected and there is no raison that the master uses the ss pin to select the communicating slave device. 12.3.5. baud rate in master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the spcon register: spr2, spr1 and spr0. the master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock. table 20 gives the different clock rates selected by spr2:spr1:spr0: table 20. spi master baud rate selection 1. clearing ssdis control bit does not clear modf. 2. special care should be taken not to set ssdis control bit when cpha = 0 because in this mode, the ss is used to start the transmission. spr2:spr1:spr0 clock rate baud rate divisor (bd) 000 f ckidle /2 2 001 f ckidle /4 4 010 f ckidle /8 8 011 f ckidle /16 16 100 f ckidle /32 32 101 f ckidleh /64 64 110 f ckidle /128 128 111 external clock output of brg
40 rev. b - november 10, 2000 preliminary t80c5111 12.4. functional description figure 16 shows a detailed structure of the spi module. figure 16. spi module block diagram 12.4.1. operating modes the serial peripheral interface can be configured as one of the two modes: master mode or salve mode. the configuration and initialization of the spi module is made through one register: the serial peripheral control register (spcon) once the spi is configured, the data exchange is made using: spcon the serial peripheral status register (spsta) the serial peripheral data register (spdat) during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sck) synchronizes shifting and sampling on the two serial data lines (mosi and miso). a slave select line ( ss) allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. when the master device transmits data to the slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex transmission with both data out and data in synchronized with the same clock (figure 17). shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic clock divider clock select /2 /4 /64 /128 spi interrupt request 8-bit bus 1-bit signal ss intclk /32 /8 /16 receive data register spdat spi control spsta cpha spr0 spr1 cpol mstr ssdis spen spr2 spcon wcol modf spif - ---- external clk
rev. b - november 10, 2000 41 preliminary t80c5111 figure 17. full-duplex master-slave interconnection 12.4.1.1. master mode the spi operates in master mode when the master bit, mstr 1 , in the spcon register is set. only one master spi device can initiate transmissions. software begins the transmission from a master spi module by writing to the serial peripheral data register (spdat). if the shift register is empty, the byte is immediately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the masters miso pin. the transmission ends when the serial peripheral transfer data flag, spif, in spsta becomes set. at the same time that spif becomes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spsta) with the spif bit set, and then reading the spdat. when the pin ss is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the spdat is resent. 12.4.1.2. slave mode the spi operates in slave mode when the master bit, mstr 2 , in the spcon register is cleared. before a data transmission occurs, the slave select pin, ss, of the slave device must be set to 0. ss must remain low until the transmission is complete. in a slave spi module, data enters the shift register under the control of the sck from the master spi module. after a byte enters the shift register, it is immediately transferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register 3 . a slave spi must complete the write to the spdat (shift register) at least one bus cycle before the master spi starts a transmission. if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. 12.4.2. transmission formats software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol 4 ) and the clock phase (cpha 4 ). cpol defines the default sck line level in idle state. it has no significant effect on the transmission format. cpha defines the edges on which the input data are sampled and the edges on which the output data are shifted (figure 18 and figure 19). the clock phase and polarity should be identical for the master spi device and the communicating slave device. 1. the spi module should be configured as a master before it is enabled (spen set). also the master spi should be configured before the slave spi. 2. the spi module should be configured as a slave before it is enabled (spen set). 3. the maximum frequency of the sck for an spi configured as a slave is the bus clock speed. 4. before writing to the cpol and cpha bits, the spi should be disabled (spen = 0). 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck v ss v dd ss ss slave mcu
42 rev. b - november 10, 2000 preliminary t80c5111 figure 18. data transmission format (cpha = 0) figure 19. data transmission format (cpha = 1) as shown in figure 18, the first sck edge is the msb capture strobe. therefore the slave must begin driving its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted (figure 20). figure 20. cpha/ ss timing figure 19 shows an spi transmission in which cpha is 1. in this case, the master begins driving its mosi pin on the first sck edge. therefore the slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmissions (figure 20). this format may be preferable in systems having only one master and only one slave driving the miso data line. msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 2 45678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
rev. b - november 10, 2000 43 preliminary t80c5111 12.4.3. error conditions the following flags in the spsta signal spi error conditions: 12.4.3.1. mode fault (modf) mode fault error in master mode spi indicates that the level on the slave select ( ss) pin is inconsistent with the actual mode of the device. modf is set to warn that there may have a multi-master conflict for system control. in this case, the spi system is affected in the following ways: an spi receiver/error cpu interrupt request is generated. the spen bit in spcon is cleared. this disable the spi. the mstr bit in spcon is cleared. when ss disable (ssdis) bit in the spcon register is cleared, the modf flag is set when the ss signal becomes 0. however, as stated before, for a system with one master, if the ss pin of the master device is pulled low, there is no way that another master is attempting to drive the network. in this case, to prevent the modf flag from being set, software can set the ssdis bit in the spcon register and therefore making the ss pin as a general purpose i/o pin. clearing the modf bit is accomplished by a read of spsta register with modf bit set, followed by a write to the spcon register. spen control bit may be restored to its original set state after the modf bit has been cleared. 12.4.3.2. write collision (wcol) a write collision (wcol) flag in the spsta is set when a write to the spdat register is done during a transmit sequence. wcol does not cause an interruption, and the transfer continues uninterrupted. clearing the wcol bit is done through a software sequence of an access to spsta and an access to spdat. 12.4.3.3. overrun condition an overrun condition occurs when the master device tries to send several data bytes and the slave devise has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read of the spdat returns this byte. all others bytes are lost. this condition is not detected by the spi peripheral. 12.4.4. interrupts two spi status flags can generate a cpu interrupt requests: table 21. spi interrupts serial peripheral data transfer flag, spif: this bit is set by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt requests. mode fault flag, modf: this bit becomes set to indicate that the level on the ss is inconsistent with the mode of the spi. modf with ssdis reset, generates receiver/error cpu interrupt requests. figure 21 gives a logical view of the above statements: flag request spif (sp data transfer) spi transmitter interrupt request modf (mode fault) spi receiver/error interrupt request (if ssdis = 0)
44 rev. b - november 10, 2000 preliminary t80c5111 figure 21. spi interrupt requests generation 12.4.5. registers there are three registers in the module that provide control, status and data storage functions. these registers are describes in the following paragraphs. 12.4.5.1. serial peripheral control register (spcon) the serial peripheral control register does the following: selects one of the master clock rates, configure the spi module as master or slave, selects serial clock polarity and phase, enables the spi module, frees the ss pin for a general purpose table 22 describes this register and explains the use of each bit: table 22. serial peripheral control register 7 6 5 4 3 2 1 0 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic r/w mode description 7 spr2 rw serial peripheral rate 2 bit with spr1 and spr0 define the clock rate 6 spen rw serial peripheral enable clear to disable the spi interface set to enable the spi interface 5 ssdis rw ss disable clear to enable ss# in both master and slave modes set to disable ss# in both master and slave modes. in slave mode, this bit has no effect if cpha = 0 4 mstr rw serial peripheral master clear to configure the spi as a slave set to configure the spi as a master 3 cpol rw clock polarity clear to have the sck set to 0 in idle state set to have the sck set to 1 in idle low 2 cpha rw clock phase clear to have the data sampled when the spsck leaves the idle state (see cpol) set to have the data sampled when the spsck returns to idle state (see cpol) ssdis modf cpu interrupt request spi receiver/error cpu interrupt request spi transmitter spi cpu interrupt request spif
rev. b - november 10, 2000 45 preliminary t80c5111 reset value= 00010100b 12.4.5.2. serial peripheral status register (spsta) the serial peripheral status register contains flags to signal the following conditions: data transfer complete write collision inconsistent logic level on ss pin (mode fault error) table 23 describes the spsta register and explains the use of every bit in the register: reset value= 00x0xxxxb table 23. serial peripheral status and control register 1 spr1 rw serial peripheral rate (spr2:spr1:spr0) 000 : f clk periph /2 001 : f clk periph /4 010 : f clk periph /8 011 : f clk periph /16 0 spr0 rw 100 : f clk periph /32 101 : f clk periph /64 110 : f clk periph /128 111 : external clock, output of brg 7 6 5 4 3 2 1 0 spif wcol - modf - - - - bit number bit mnemonic r/w mode description 7 spif r serial peripheral data transfer flag clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. 6 wcol r write collision flag cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. set by hardware to indicate that a collision has been detected. 5-rw reserved the value read from this bit is indeterminate. do not set this bit 4 modf r mode fault cleared by hardware to indicate that the ss pin is at appropriate logic level, or has been approved by a clearing sequence. set by hardware to indicate that the ss pin is at inappropriate logic level 3-rw reserved the value read from this bit is indeterminate. do not set this bit 2-rw reserved the value read from this bit is indeterminate. do not set this bit 1-rw reserved the value read from this bit is indeterminate. do not set this bit 0-rw reserved the value read from this bit is indeterminate. do not set this bit bit number bit mnemonic r/w mode description
46 rev. b - november 10, 2000 preliminary t80c5111 12.4.5.3. serial peripheral data register (spdat) the serial peripheral data register (table 24) is a read/write buffer for the receive data register. a write to spdat places data directly into the shift register. no transmit buffer is available in this model. a read of the spdat returns the value located in the receive buffer and not the content of the shift register. table 24. serial peripheral data register reset value= xxxx xxxxb r7:r0 : receive data bits spcon, spsta and spdat registers may be read and written at any time while there is no on-going exchange. however, special care should be taken when writing to them while a transmission is on-going: do not change spr2, spr1 and spr0 do not change cpha and cpol do not change mstr clearing spen would immediately disable the peripheral writing to the spdat will cause an overflow 7 6 5 4 3 2 1 0 r7 r6 r5 r4 r3 r2 r1 r0
rev. b - november 10, 2000 47 preliminary t80c5111 13. programmable counter array pca the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accuracy. the pca consists of a dedicated timer/ counter which serves as the time base for an array of five compare/ capture modules. its clock input can be programmed to count any one of the following signals: oscillator frequency ? 12 ( ? 6 in x2 mode) oscillator frequency ? 4( ? 2 in x2 mode) timer 0 overflow external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. module 4 can also be programmed as a watchdog timer (see section "pca watchdog timer", page 56). when the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/o. these pins are listed below. if the port is not used for the pca, it can still be used for standard i/o. the pca timer is a common time base for all five modules (see figure 22). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see table 25) and can be programmed to run at: 1/12 the oscillator frequency. (or 1/6 in x2 mode) 1/4 the oscillator frequency. (or 1/2 in x2 mode) the timer 0 overflow. the input on the eci pin (p1.2). pca component external i/o pin 16-bit counter p1.2 / eci 16-bit module 0 p1.3 / cex0 16-bit module 1 p1.4 / cex1 16-bit module 2 p1.5 / cex2 16-bit module 3 p1.6 / cex3 16-bit module 4 p1.7 / cex4
48 rev. b - november 10, 2000 preliminary t80c5111 figure 22. pca timer/counter table 25. cmod: pca counter mode register cmod address 0d9h cidl wdte - - - cps1 cps0 ecf reset value 0 0 x x x 0 0 0 symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cid l = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input. b b. f osc = oscillator frequency 0 0 internal clock f osc /12 ( or f osc /6 in x2 mode). 0 1 internal clock f osc /4 ( or f osc /2 in x2 mode). 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = f osc /8) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ec f = 0 disables that function of cf. cidl cps1 cps0 ecf it ch cl 16 bit up/down counter to pca modules fosc /12 fosc / 4 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 over?ow
rev. b - november 10, 2000 49 preliminary t80c5111 the cmod sfr includes three additional bits associated with the pca (see figure 22 and table 25). the cidl bit which allows the pca to stop during idle mode. the wdte bit which enables or disables the watchdog function on module 4. the ecf bit which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to table 26). bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. bit cf: the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. table 26. ccon: pca counter control register the watchdog timer function is implemented in module 4 (see figure 25). the pca interrupt system is shown in figure 23 ccon address 0d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 reset value 0 0 x 0 0 0 0 0 symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software.
50 rev. b - november 10, 2000 preliminary t80c5111 figure 23. pca interrupt system pca modules: each one of the five compare/capture modules has six possible functions. it can perform: 16-bit capture, positive-edge triggered, 16-bit capture, negative-edge triggered, 16-bit capture, both positive and negative-edge triggered, 16-bit software timer, 16-bit high speed output, 8-bit pulse width modulator. in addition, module 4 can be used as a watchdog timer. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 27). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. table 28 shows the ccapmn settings for the various pca functions. cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea
rev. b - november 10, 2000 51 preliminary t80c5111 table 27. ccapmn: pca modules compare/capture control registers table 28. pca module modes (ccapmn registers) there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 29 & table 30) ccapmn address n=0-4 ccapm0=0dah ccapm1=0dbh ccapm2=0dch ccapm3=0ddh ccapm4=0deh - ecomn cappn capnn matn togn pwmm eccfn reset value x 0 0 0 0 0 0 0 symbol function - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. ecomn cappn capnn matn togn pwmm eccfn module function 0 0 0 0 0 0 0 no operation x10000x 16-bit capture by a positive-edge trigger on cexn x01000x 16-bit capture by a negative trigger on cexn x 1 1 0 0 0 x 16-bit capture by a transition on cexn 100100x 16-bit software timer / compare mode. 1 0 0 1 1 0 x 16-bit high speed output 1 0 0 0 0 1 0 8-bit pwm 1 0 0 1 x 0 x watchdog timer (module 4 only)
52 rev. b - november 10, 2000 preliminary t80c5111 table 29. ccapnh: pca modules capture/compare registers high table 30. ccapnl: pca modules capture/compare registers low table 31. ch: pca counter high table 32. cl: pca counter low 13.1. pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated (refer to figure 24). ccapnh address n=0-4 ccap0h=0fah ccap1h=0fbh ccap2h=0fch ccap3h=0fdh ccap4h=0feh 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 ccapnl address n=0-4 ccap0l=0eah ccap1l=0ebh ccap2l=0ech ccap3l=0edh ccap4l=0eeh 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 ch address 0f9h 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 cl address 0e9h 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0
rev. b - november 10, 2000 53 preliminary t80c5111 figure 24. pca capture mode 13.2. 16-bit software timer / compare mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 25). cf cr ccon 0xd8 ch cl ccapnh ccapnl ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca counter/timer ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture
54 rev. b - november 10, 2000 preliminary t80c5111 figure 25. pca compare mode and pca watchdog timer before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, otherwise an unwanted match could happen. writing to ccapnh will set the ecom bit. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesnt occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. 13.3. high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 26). a prior write must be done to ccapnl and ccapnh before writing the ecomn bit. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16 bit comparator match ccon 0xd8 pca it enable pca counter/timer reset * cidl cps1 cps0 ecf cmod 0xd9 wdte * only for module 4 reset write to ccapnl write to ccapnh cf ccf2 ccf1 ccf0 cr ccf3 ccf4 10
rev. b - november 10, 2000 55 preliminary t80c5111 figure 26. pca high speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, otherwise an unwanted match could happen. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesnt occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. 13.4. pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 27 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16 bit comparator match cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer write to ccapnh reset write to ccapnl 1 0
56 rev. b - november 10, 2000 preliminary t80c5111 sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. figure 27. pca pwm mode 13.5. pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 25 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. this watchdog timer wont generate a reset out on the reset pin. cl ccapnh ccapnl ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8 bit comparator cexn 0 1 3 < enable pca counter/timer over?ow
rev. b - november 10, 2000 57 preliminary t80c5111 14. analog-to-digital converter (adc) 14.1. introduction this section describes the on-chip 10 bit analog-to-digital converter of the t80c5111. eight adc channels are available for sampling of the external sources an0 to an7. an analog multiplexer allows the single adc converter to select one from the 8 adc channels as adc input voltage (adcin). adcin is converted by the 10 bit- cascaded potentiometric adc. three kind of conversion are available: standard conversion (7-8 bits). precision conversion (8-9 bits). accurate conversion (10 bits). for the precision conversion, set bits psidle and adsst in adcon register to start the conversion. the chip is in a idle mode, the cpu doesnt run but the peripherals are always running. this mode allows digital noise to be lower, to ensure precise conversion. for the accurate conversion, set bits quietm and adsst in adcon register to start the conversion. the chip is in a pseudo-idle mode, the ad is the only peripheral running. this mode allows digital noise to be as low as possible, to ensure high precision conversion. for these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. if another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. 14.2. features 8 channels with multiplexed inputs 10-bit cascaded potentiometric adc conversion time 40 micro-seconds zero error (offset) +/- 2 lsb max external positive reference voltage range 2.4 to vcc internal positive reference voltage 2.4 volt. if vref is used as output, the load must be higher than 18 kohm. adcin range 0 to vcc integral non-linearity typical 1 lsb, max. 2 lsb differential non-linearity typical 0.5 lsb, max. 1 lsb conversion complete flag or conversion complete interrupt selected adc clock 14.3. adc i/o functions ainx are general i/o that are shared with the adc channels. the channel select bit in adcf register define which adc channel pin will be used as adcin. the remaining adc channels pins can be used as general purpose i/o or as the alternate function that is available. writes to the port register which arent selected by the adcf will not have any effect.
58 rev. b - november 10, 2000 preliminary t80c5111 figure 28. adc description figure 29 shows the timing diagram of a complete conversion. for simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. for adc characteristics and timing parameters refer to the section ac characteristics of the t80c5111 datasheet. figure 29. timing diagram note: tsetup = 4 us 14.4. adc converter operation a start of single a/d conversion is triggered by setting bit adsst (adcon.3). the busy flag adsst(adcon.3) remains set as long as an a/d conversion is running. after completion of the a/d conversion, it is cleared by hardware. when a conversion is running, this flag can be read only, a write has no effect. ain0/p4.0 ain1/p4.1 ain2/p4.2 ain3/p4.3 ain4/p4.4 ain5/p4.5 ain6/p4.6 ain7/p4.7 000 001 010 011 100 101 110 111 sch2 adcon.2 sch0 adcon.0 sch1 adcon.1 conv_ck aden adcon.5 adsst adcon.3 adeoc adcon.4 adc interrupt request eadc ie1.1 control avss sample and hold addh vref r/2r dac 8 10 + - addl 2 sar adcin vagnd selref adclk.7 2.4v vadref aden adcon.5 aden adsst adeoc t setup t conv conv_ck
rev. b - november 10, 2000 59 preliminary t80c5111 the end-of-conversion flag adeoc (adcon.4) is set when the value of conversion is available in addh and addl, it is cleared by software. if the bit eadc (ie1.1) is set, an interrupt occur when flag adeoc is set (see figure 31). clear this flag for re-arming the interrupt. the bits sch0 to sch2 in adcon register are used for the analog input channel selection. before starting normal power reduction modes the adc conversion has to be completed. table 33. selected analog input 14.5. voltage conversion when the adcin is equals to varef the adc converts the signal to 3ffh (full scale). if the input voltage equals vagnd, the adc converts it to 000h. input voltage between varef and vagnd are a straight-line linear conversion. all other voltages will result in 3ffh if greater than varef and 000h if less than vagnd. note that adcin should not exceed varef absolute maximum range. 14.6. clock selection the maximum clock frequency for adc (conv_ck for conversion clock) is defined in the ac characteristics section. a prescaler is featured (adcclk) to generate the conv_ck clock from the oscillator frequency. figure 30. a/d converter clock sch2 sch1 sch0 selected analog input 0 0 0 an0 0 0 1 an1 0 1 0 an2 0 1 1 an3 1 0 0 an4 1 0 1 an5 1 1 0 an6 1 1 1 an7 prescaler adclk a/d converter conv_ck ckadc / 2
60 rev. b - november 10, 2000 preliminary t80c5111 14.7. adc standby mode when the adc is not used, it is possible to set it in standby mode by clearing bit aden in adcon register. in this mode the power dissipation is about 1uw. 14.8. voltage referencee the voltage reference can be either internal or external. as input, the vref pin is used to enter the voltage reference for the a/d conversion. when the voltage reference is active, the vref pin is an output. this voltage can be used for the a/d and for any other application requiring a voltage independant from the power supply. voltage typical value is 2.4 volt and the load must greater than 18 koms. 14.9. it adc management an interrupt end-of-conversion will occurs when the bit adeoc is actived and the bit eadc is set. for re-arming the interrupt the bit adeoc must be cleared by software. figure 31. adc interrupt structure 14.10. registers table 34. adcon register adcon (s:f3h) adc control register 7 6 5 4 3 2 1 0 quietm psidle aden adeoc adsst sch2 sch1 sch0 bit number bit mnemonic description 7 quietm pseudo idle mode (best precision) set to put in quiet mode during conversion. cleared by hardware after completion of the conversion. 6 psidle pseudo idle mode (good precision) set to put in idle mode during conversion. cleared by hardware after completion of the conversion. adeoc adcon.2 eadc ie1.1 adci
rev. b - november 10, 2000 61 preliminary t80c5111 reset value=x000 0000b table 35. adclk register adclk (s:f2h) adc clock prescaler reset value: 0000 0000b table 36. addh register addh (s:f5h read only) adc data high byte register read only register reset value: 00h 5 aden enable/ standby mode set to enable adc. clear for standby mode (power dissipation 1 uw). 4 adeoc end of conversion set by hardware when adc result is ready to be read. this flag can generate an interrupt. must be cleared by software. 3 adsst start and status set to start an a/d conversion. cleared by hardware after completion of the conversion. 2-0 sch2:0 selection of channel to convert see table 33. 7 6 5 4 3 2 1 0 selref prs 6 prs 5 prs 4 prs 3 prs 2 prs 1 prs 0 bit number bit mnemonic description 7 selref selection and activation of the internal 2.4v voltage reference set to enable the internal voltage reference. clear to disable the internal voltage reference. 6-0 prs6:0 clock prescaler f conv_ck =f ckadc / (2 * prs) if prs=0, f conv_ck =f ckadc / 256 7 6 5 4 3 2 1 0 adat 9 adat 8 adat 7 adat 6 adat 5 adat 4 adat 3 adat 2 bit number bit mnemonic description 7-0 adat9:2 adc result bits 9-2 bit number bit mnemonic description
62 rev. b - november 10, 2000 preliminary t80c5111 table 37. addl register addl (s:f4h read only) adc data low byte register read only register reset value: xxxx xx00b table 38. adcf register adcf (s:f6h) adc input select register reset value=0000 0000b 7 6 5 4 3 2 1 0 ------ adat 1 adat 0 bit number bit mnemonic description 7-6 - reserved the value read from these bits are indeterminate. do not set these bits. 1-0 adat1:0 adc result bits 1-0 7 6 5 4 3 2 1 0 sel7 sel6 sel5 sel4 sel3 sel2 sel1 sel0 bit number bit mnemonic description 7-0 sel7-0 select input 7-0 set to select bit 7-0 as possible input for a/d cleared to leave this bit free for other function
rev. b - november 10, 2000 63 preliminary t80c5111 15. interrupt system the t80c5111 has a total of 8 interrupt vectors: two external interrupts ( int0 and int1), two timer interrupts (timers 0, 1), serial port interrupt, pca, spi and a/d. these interrupts are shown in figure 32.. figure 32. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (see table 41.). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the interrupt priority register (see table 43.) and in the interrupt priority high register (see table 45.). table 39. shows the bit values and priority levels associated with each combination. ie1 0 3 high priority interrupt interrupt polling sequence low priority interrupt global disable individual enable ti ri tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 nc spi 0 3 adc 0 3 0 3 cf ccfx pca
64 rev. b - november 10, 2000 preliminary t80c5111 a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cant be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 39. priority bit level values iph.x ip.x interrupt level priority 0 0 0 (lowest) 0 1 1 1 0 2 1 1 3 (highest) table 40. address vectors interrupt name interrupt address vector priority number external interrupt (int0) 0003h 1 timer0 (tf0) 000bh 2 external interrupt (int1) 0013h 3 timer1 (tf1) 001bh 4 pca (cf or ccfn) 0033h 5 uart (ri or ti) 0023h 6 spi 004bh 8 adc 0043h 9
rev. b - november 10, 2000 65 preliminary t80c5111 reset value = 00x0 0000b bit addressable table 41. ie register ie - interrupt enable register (a8h) 7 6 5 4 3 2 1 0 ea ec - es et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 ec pca interrupt enable clear to disable the the pca interrupt. set to enable the the pca interrupt. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3 et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1 et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
66 rev. b - november 10, 2000 preliminary t80c5111 reset value = xxxx x00xb no bit addressable table 42. ie1 register ie1 (s:c0h) interrupt enable register 7 6 5 4 3 2 1 0 - - - - - espi eadc - bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 espi spi interrupt enable bit clear to disable the spi interrupt. set to enable the spi interrupt. 1 eadc a/d interrupt enable bit clear to disable the adc interrupt. set to enable the adc interrupt. 0 - reserved the value read from this bit is indeterminate. do not set this bit.
rev. b - november 10, 2000 67 preliminary t80c5111 reset value = x0x0 0000b bit addressable. table 43. ipl0 register ipl0 - interrupt priority register (b8h) 7 6 5 4 3 2 1 0 - ppc - ps pt1 px1 pt0 px0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 ppcl pca counter interrupt priority bit refer to ppch for priority level 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 psl serial port priority bit refer to psh for priority level. 3 pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2 px1l external interrupt 1 priority bit refer to px1h for priority level. 1 pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0 px0l external interrupt 0 priority bit refer to px0h for priority level.
68 rev. b - november 10, 2000 preliminary t80c5111 reset value = xxxx x00xb not bit addressable. table 44. ipl1 register ipl1 - interrupt priority low register 1 (s:b2h) 7 6 5 4 3 2 1 0 - - - - - pspi padc - bit number bit mnemonic description 7 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 pspi spi interrupt priority level less significant bit. refer to pspih for priority level. 1 padc adc interrupt priority level less significant bit. refer to padch for priority level. 0 - reserved the value read from this bit is indeterminate. do not set this bit.
rev. b - november 10, 2000 69 preliminary t80c5111 reset value = x0x0 0000b not bit addressable table 45. iph0 register iph0 - interrupt priority high register (b7h) 7 6 5 4 3 2 1 0 - ppch - psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 ppch pca counter interrupt priority level most significant bit ppch ppc priority level 0 0 lowest 01 10 1 1 highest priority 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 psh serial port priority high bit psh ps priority level 0 0 lowest 01 10 1 1 highest 3 pt1h timer 1 overflow interrupt priority high bit pt1h pt1 priority level 0 0 lowest 01 10 1 1 highest 2 px1h external interrupt 1 priority high bit px1h px1 priority level 0 0 lowest 01 10 1 1 highest 1 pt0h timer 0 overflow interrupt priority high bit pt0h pt0 priority level 0 0 lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0 priority level 0 0 lowest 01 10 1 1 highest
70 rev. b - november 10, 2000 preliminary t80c5111 reset value = xxxx x00xb not bit addressable table 46. iph1 register iph1 - interrupt priority high register 1 (b3h) 7 6 5 4 3 2 1 0 - - - - - pspih padch - bit number bit mnemonic description 7 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 pspih spi interrupt priority level most significant bit pspih pspi priority level 0 0lowest 01 10 1 1highest 1 padch adc interrupt priority level most significant bit padch padc priority level 0 0lowest 01 10 1 1highest 0 - reserved the value read from this bit is indeterminate. do not set this bit.
rev. b - november 10, 2000 71 preliminary t80c5111 16. rom 16.1. rom structure the t80c5111 rom memory is divided in three different arrays: the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kbytes. the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 16.2. rom lock system the program lock system, when programmed, protects the on-chip program against software piracy. 16.2.1. encryption array within the rom array are 64 bytes of encryption array. every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. when using the encryption array, one important factor needs to be considered. if a byte has the value ffh, verifying the byte will produce the encryption byte value. if a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. for this reason all the unused code bytes should be programmed with random values. 16.2.2. configuration byte the configuration byte is a special register. its content, described in paragraph 6.6.1. is defined by the diffusion mask in the rom version or written by the otp programmer in the otp version. the lock bits when programmed according to table 41. will provide different level of protection for the on-chip code and data. u: unprogrammed p: programmed *warning: when security bit is set, rom contend cannot be verified. only the crc is verified. 16.2.3. signature bytes the t80c5111 contains 4 factory programmed signatures bytes. to read these bytes, perform the process described in section signature bytes content, page 89. 16.2.4. verify algorithm refer to section verifying algorithm, page 85 table 47. program lock bits program lock bits protection description security level lb1 lb2 1 u u no program lock features enabled. code verify will still be encrypted by the encryption array if programmed. movc instruction returns non encrypted data. 2 p u same as 1 3 u p same as 2, also verify is disabled this security level is available because rom integrity will be veri?ed thanks to another method*.
72 rev. b - november 10, 2000 preliminary t80c5111 16.3. program code mapping as there is no external capability in lpc packages, the code size is limited to 4 kbytes. any access above 4k will be mapped in the first 4k segment (0xxxh).
rev. b - november 10, 2000 73 preliminary t80c5111 17. eprom 17.1. eprom programming specific algorithm is implemented,. pleas use qualified device programmers from third party vendors. 17.2. eprom erasure (windowed packages only) erasing the eprom erases the code array, the encryption array and the lock bits returning the parts to full functionality. erasure leaves all the eprom cells in a 1s state (ff). 17.2.1. erasure characteristics the recommended erasure procedure is exposure to ultraviolet light (at 2537 ?) to an integrated dose at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. an exposure of 1 hour is recommended with most of standard erasers. erasure of the eprom begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 ?. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. 17.3. signature bytes 17.3.1. signature bytes content the t80c5111 has four signature bytes in location 30h, 31h, 60h and 61h. to read these bytes follow the procedure for eprom signature bytes reading. table 48. shows the content of the signature byte for the t80c5111. table 48. signature bytes content location contents comment 30h 58h manufacturer code: atmel wireless & microcontrollers 31h 57h family code: c51 x2 60h 2eh product name: t80c5111 4k rom version 60h aeh product name: t80c5111 4k otp version 61h efh product revision number : t80c5111 rev.0
74 rev. b - november 10, 2000 preliminary t80c5111 18. electrical characteristics 18.1. absolute maximum ratings (1) ambiant temperature under bias: c = commercial 0 cto70 c i = industrial -40 cto85 c storage temperature-65 cto+150 c voltage on v cc to v ss -0.5vto+7v voltage on v pp to v ss -0.5vto+13v voltage on any pin to v ss -0.5vtov cc + 0.5 v power dissipation1 w (2) notes 1. s tresses at or above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is speci?cation is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package. 18.2. power consumption measurement since the introduction of the first c51 devices, every manufacturer made operating icc measurements under reset, which made sense for the designs were the cpu was running under reset. in our new devices, the cpu is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. thats why, while keeping measurements under reset, we present a new way to measure the operating icc: using an internal test rom, the following code is executed: label: sjmp label (80 fe) ports 1, 3, 4 are disconnected, rst = vcc, xtal2 is not connected and xtal1 is driven by the clock. this is much more representative of the real operating icc.
rev. b - november 10, 2000 75 preliminary t80c5111 18.3. dc parameters for standard voltage t a =0 cto+70 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. t a = -40 cto+85 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. table 49. dc parameters in standard voltage 18.4. dc parameters for low voltage t a =0 cto+70 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. t a = -40 cto+85 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 3, 4. (6) 0.3 0.45 1.0 v v v i ol = 100 m a i ol = 1.6 ma i ol = 3.5 ma v oh output high voltage, ports 1, 3, 4. (6) mode pseudo bidirectionnel v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 m a i oh = -30 m a i oh = -60 m a v cc = 5 v 10% v oh2 output high voltage, ports 1, 3, 4. (6) mode push pull v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -100 m a i oh = -1.6 ma i oh = -3.2 ma v cc = 5 v 10% r rst rst pullup resistor 50 90 (5) 200 k w i il logical 0 input current ports 1, 3 and 4 -50 tbd m a vin = 0.45 v, port 1 & 3 vin = 0.45 v, port 4 i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 3, 4 -650 m a vin = 2.0 v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current to be con?rmed 20 (5) 50 m a 2.0 v < v cc < 5.5 v (3) i cc under reset power supply current maximum values, x1 mode: (7) to be con- ?rmed 3+ 0.4 freq (mhz) @12mhz 5.8 @16mhz 7.4 ma v cc = 5.5 v (1) i cc operating power supply current maximum values, x1 mode: (7) to be con- ?rmed 3 + 0.6 freq (mhz) @12mhz 10.2 @16mhz 12.6 ma v cc = 5.5 v (8) i cc idle power supply current maximum values, x1 mode: (7) to be con- ?rmed 3+0.3 freq (mhz) @12mhz 3.9 @16mhz 5.1 ma v cc = 5.5 v (2) v ret supply voltage during power down mode 2 v v rst+ high threshold of power fail detect 2.54 v v rst low threshold of power fail detect 2.19 v
76 rev. b - november 10, 2000 preliminary t80c5111 table 50. dc parameters for low voltage notes 1. i cc under reset is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 37.), v il = v ss + 0.5 v, v ih = v cc - 0.5v; xtal2 n.c.; vpp = rst = v cc . i cc would be slightly higher if a crystal oscillator used 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch ,t chcl = 5 ns, v il =v ss + 0.5 v, v ih =v cc - 0.5 v; xtal2 n.c; vpp = rst = v ss (see figure 35.). 3. power down i cc is measured with all output pins disconnected; vpp = v ss ; xtal2 nc.; rst = v ss (see figure 36.). 4. not applicable 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 6. if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. 7. for other values, please contact your sales of?ce. 8. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 37.), v il = v ss + 0.5 v, v ih =v cc - 0.5v; xtal2 n.c.; rst/vpp= v cc ;. the internal rom runs the code 80 fe (label: sjmp label). i cc would be slightly higher if a crystal oscillator is used. measurements are made with otp products when possible, which is the worst case. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 3, 4 (6) 0.3 0.45 1.0 v v v i ol = i ol = 0.8 ma i ol = v oh output high voltage, ports 1, 3, 4. (6) 0.9 v cc v cc - 0.7 v cc - 1.5 v v v i oh = -10 m a i oh = - ma i oh = - ma v oh2 output high voltage, ports 1, 3, 4. (6) mode push pull 0.9v cc v cc - 0.7 v cc - 1.5 v v v i oh = -100 m a i oh = - ma i oh = - ma i il logical 0 input current ports 1, 2 and 3 -50 tbd m a vin = 0.45 v, port 1 & 3 vin = 0.45 v, port 4 i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 3, 4 -650 m a vin = 2.0 v r rst rst pullup resistor 50 90 (5) 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current to be con?rmed 20 (5) 10 (5) 50 30 m a v cc = 2.0 v to 5.5 v (3) v cc = 2.0 v to 3.3 v (3) i cc under reset power supply current maximum values, x1 mode: (7) to be con- ?rmed 1.5 + 0.2 freq (mhz) @12mhz 3.4 @16mhz 4.2 ma v cc = 3.3 v (1) i cc operating power supply current maximum values, x1 mode: (7) to be con- ?rmed 1.5 + 0.3 freq (mhz) @12mhz 4.6 @16mhz 5.8 ma v cc = 3.3 v (8) i cc idle power supply current maximum values, x1 mode: (7) to be con- ?rmed 1.5+0.15 freq (mhz) @12mhz 2 @16mhz 2.6 ma v cc = 3.3 v (2) v ret supply voltage during power down mode 2 v v rst+ high threshold of power fail detect 2.54 v v rst low threshold of power fail detect 2.19 v
rev. b - november 10, 2000 77 preliminary t80c5111 figure 33. i cc test condition, under reset figure 34. operating i cc test condition figure 35. i cc test condition, idle mode v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc reset = vss after a high pulse during at least 24 clock cycles v cc rst xtal2 xtal1 v ss v cc i cc (nc) v cc all other pins are disconnected. clock signal reset = vss after a high pulse during at least 24 clock cycles v cc
78 rev. b - november 10, 2000 preliminary t80c5111 figure 36. i cc test condition, power-down mode figure 37. clock signal waveform for i cc tests in active and idle modes 18.5. dc parameters for a/d converter t a =0 cto+70 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. t a = -40 cto+85 c; v ss =0v;v cc =2.7vto5.5v;f=0to30 mhz. table 51. dc parameters for low voltage notes: (1) total drift on one part over full voltage and temperature range is below 20 mv. . 18.6. ac parameters 18.6.1. explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. symbol parameter min typ max unit test conditions resolution 10 bit avi n analog input voltage vss- 0.2 vcc + 0.2 v rref resistance between vref and vss 13 18 24 kohm vref value of integrated voltage source 2.43 2.49 v small variation with vcc and temperature (1) lref load on integrated voltage source 10 kohm cai analog input capacitance 60 pf during sampling integral non linearity 1 2 lsb differential non linearity 0.5 1 lsb offset error -2 2 lsb input source impedance 1 kohm for 10 bit resolution at maximum speed rst xtal2 xtal1 v ss v cc i cc v cc reset = vss after a high pulse during at least 24 clock cycles v cc all other pins are disconnected. v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch =t chcl = 5ns.
rev. b - november 10, 2000 79 preliminary t80c5111 example:t xhdv = time from clock rising edge to input data valid. t a =0to+70 c (commercial temperature range); v ss =0v;v cc =5v 10%; -v ranges. t a =0to+70 c (commercial temperature range); v ss =0v;2.7v 80 rev. b - november 10, 2000 preliminary t80c5111 table 55. ac parameters for a fix clock table 56. ac parameters for a variable clock: derating formula 18.6.3. shift register timing waveforms figure 38. shift register timing waveforms 18.6.4. external clock drive characteristics (xtal1) speed -v x2 mode 33 mhz 66 mhz equiv. -v standard mode 40 mhz -l x2 mode 20 mhz 40 mhz equiv. -l standard mode 40 mhz units symbol min max min max min max min max t xlxl 180 300 300 300 ns t qvhx 100 200 200 200 ns t xhqx 10 30 30 30 ns t xhdx 0 0 0 0 ns t xhdv 17 117 117 117 ns symbol type standard clock x2 clock -v -l units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 50 ns t xhqx min 2 t - x t - x 20 20 ns t xhdx min x x 0 0 ns t xhdv max 10 t - x 5 t- x 133 133 ns symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % valid valid input data valid valid 0123456 8 7 clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri 01234567 valid valid valid valid instruction
rev. b - november 10, 2000 81 preliminary t80c5111 18.6.5. external clock drive waveforms figure 39. external clock drive waveforms 18.6.6. a/d comverter notes: (1)for 10 bits resolution 18.6.7. ac testing input/output waveforms figure 40. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic 1 and 0.45v for a logic 0. timing measurement are made at v ih min for a logic 1 and v il max for a logic 0. 18.6.8. float waveforms figure 41. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 3 20ma. symbol parameter min typ max units conversion time 11 clock periods (1 for sam- pling, 10 for conversion) fconv_ck clock conversion frequency 350 (1) khz sampling frequency 8 32 khz v cc -0.5 v 0.45 v 0.7v cc 0.2v cc -0.1 v t chcl t clcx t clcl t clch t chcx 0.45 v v cc -0.5 v 0.2v cc +0.9 0.2v cc -0.1 input/output v ol +0.1 v v oh -0.1 v float v load v load +0.1 v v load -0.1 v
82 rev. b - november 10, 2000 preliminary t80c5111 18.6.9. clock waveforms valid in normal clock mode. in x2 mode xtal2 signal must be changed to xtal2 divided by two. figure 42. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. clock xtal2 internal state4 state5 state6 state1 state2 state3 state4 state5 serial por t shift clock por t opera tion txd (mode 0) rxd sampled rxd sampled p1, p3, p4 pins sampled p1, p3, p4 pins sampled mov dest port (p1, p3, p4) (includes int0, int1, to, t1) old data new data p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2
rev. b - november 10, 2000 83 preliminary t80c5111 19. ordering information table 57. maximum clock frequency notes: -l parts supplied vith 5v +-10% have same speed and timing as -v parts code -v -l unit standard mode, oscillator frequency standard mode, internal frequency 40 40 40 40 mhz x2 mode, oscillator frequency x2 mode, internal equivalent frequency 33 66 20 40 mhz packages: td : so24 tg : so20 3z: dil24 cz: cdil24 window* ib: ssop16 t part number 83c5111 zzz (4k rom, zzz is the customer code) 87c5111 (4k otp, zzz is the customer code if factory programmed) conditioning s: stick r:tape & reel u: stick and dry pack f:tape & reel and dry pack r (*) check with atmel wireless & microcontrollers sales of?ce for availability 87c5111 -3z c temperature range c:commercial 0 to 70 o c i:industrial -40 to 85 o c e: engineering samples v:vcc: 5v +/- 10% l: vcc: 2.7-5.5 v v
84 rev. b - november 10, 2000 preliminary t80c5111 table 58. possible order entries exten- sion type t83c5111 mask rom t87c5111 otp -3zscl dil24, stick, comm. 2.7-5.5v, 40 mhz -3zscv dil24, stick, comm. 5v, 66mhz -3zsil dil24, stick, ind. 2.7-5.5v, 40 mhz x x -tdscl so24, stick, comm. 2.7-5.5v, 40 mhz -tdscv so24, stick, comm. 5v, 66mhz -tdsil so24, stick, ind. 2.7-5.5v, 40 mhz x x -tdrcl so24, tape & reel, comm. 2.7-5.5v, 40 mhz -tdrcv so24, tape & reel, comm. 5v, 66mhz -tdril so24, tape & reel, ind. 2.7-5.5v, 40 mhz x x -tgscl so20, stick, comm. 2.7-5.5v, 40 mhz -tgscv so20, stick, comm. 5v, 66mhz -tgsil so20, stick, ind. 2.7-5.5v, 40 mhz -tgrcl so20, tape & reel, comm. 2.7-5.5v, 40 mhz -tgrcv so20, tape & reel, comm. 5v, 66mhz -tgril so20, tape & reel, ind. 2.7-5.5v, 40 mhz -ibucl ssop16, stick & dry pack, comm. 2.7-5.5v, 40 mhz -ibucv ssop16, stick & dry pack, comm. 5v, 66mhz -ibuil ssop16, stick & dry pack, ind. 2.7-5.5v, 40 mhz x x -ibfcl ssop16, tape & reel & dry pack, comm. 2.7-5.5v, 40 mhz -ibfcv ssop16, tape & reel & dry pack, comm. 5v, 66mhz -ibfil ssop16, tape & reel & dry pack, ind. 2.7-5.5v, 40 mhz x x -icucl ssop24, stick & dry pack, comm. 2.7-5.5v, 40 mhz -icucv ssop24, stick & dry pack, comm. 5v, 66mhz -icuil ssop24, stick & dry pack, ind. 2.7-5.5v, 40 mhz -icfcl ssop24, tape & reel & dry pack, comm. 2.7-5.5v, 40 mhz -icfcv ssop24, tape & reel & dry pack, comm. 5v, 66mhz -icfil ssop24, tape & reel & dry pack, ind. 2.7-5.5v, 40 mhz -tdsel engineering sample, so24, stick, 2.7-5.5v, 40mhz x -czsel engineering sample, ceramic windowed dil24, stick, 2.7-5.5v, 40mhz x

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